1. Field of the Invention
The invention relates generally to a method of manufacturing a flash memory device. More particularly, the invention relates to a method of manufacturing a flash memory device, which can prevent damage of a semiconductor substrate during an ion injection process for forming a junction region.
2. Description of the Prior Art
Generally, a flash memory cell includes a floating gate formed on and electrically separated from the semiconductor substrate, a control gate electrically formed on the floating gate and also separated from the floating gate by a dielectric film, and a junction region formed on the semiconductor substrate at both sides of the floating gate. A method of manufacturing a flash memory device having this memory cell will be explained.
FIGS. 1A-1E are cross-sectional views of a device for explaining a method of manufacturing a conventional flash memory device, which will be explained by reference to FIGS. 2A-2D.
FIG. 1A is a cross-sectional view of a device in which a device separation film 2 is formed in a field region of a semiconductor substrate 1, and FIG. 2A shows a layout of FIG. 1A.
FIG. 1B shows a cross-sectional view of the device. After a tunnel oxide film 3 and a first polysilicon layer are sequentially formed on the entire structure, they are patterned to form a floating gate 4. The floating gate 4 is patterned in the Y direction, as shown in FIG. 2B.
Referring to FIG. 1C, after a dielectric film 5 is formed on the entire structure and is then cured by an annealing process, a second polysilicon layer 6a, a tungsten silicide layer 6b, and a reflection prevention film 6c are sequentially formed on the dielectric film 5. Then, the reflection prevention film 6c, the tungsten silicide layer 6b, the second polysilicon layer 6a, and the dielectric film 5 are sequentially patterned to form a control gate including the second polysilicon layer 6a and the tungsten silicide layer 6b. The control gate is patterned in the X direction.
FIG. 1D is a cross-sectional view of the device in which a first mask 7 is formed so that the semiconductor substrate 1 in the portion in which a source region will be formed can be exposed, the device separation film 2 in the exposed portion (section B in FIG. 2C) is removed and impurity ions are then injected into the exposed portion of the semiconductor substrate 1, thus forming a source region 8, which shows a cross-sectional view of the device taken along lines A1-A2 in FIG. 2C. At this time, the source region 8 forms a line shape extending in the X direction, as shown in FIG. 2C.
FIG. 1E is a cross-sectional view of the device in which, after the first mask 7 is removed, a second mask 9 is formed so that the semiconductor substrate 1 in the portion in which a drain region will be formed and impurity ions are injected into the exposition portion of the semiconductor substrate 1, thus forming a drain region 10, which shows a cross-sectional view of the device taken along lines C1-C2 in FIG. 2D.
Next, after the second mask 9 is formed, an annealing process is performed to the impurity ions injected into the source region 8 and the drain region 10.
In the conventional method, however, as the semiconductor substrate at the portion from which the dielectric film is removed is exposed during a self-alignment etching process for forming the control gate, it tends to damage the semiconductor substrate due to the etching. Further, as the ion injection process for forming the source region and the drain region is performed with the damaged semiconductor substrate being exposed, dopants are damaged and the injected ions become non-uniformly distributed.
Therefore, the threshold voltage (Vth) of the memory cell varies due to damage of the dopants and non-uniformity of the concentration and the operating speed of the device is lowered, thus resulting in degrading reliability of the device.
A method of manufacturing a flash memory device includes the steps of sequentially forming a tunnel oxide film and a first polysilicon layer on a semiconductor substrate in which a device separation film is formed and then patterning the tunnel oxide film and the first polysilicon layer to form a floating gate; forming a mask so that a portion in which a source region will be formed can be exposed and then removing the device separation film at the exposed position; forming a dielectric film including a lower oxide film, a nitride film and an upper oxide film on the entire structure, performing an annealing process, and then forming a second polysilicon layer on the dielectric film; sequentially removing the polysilicon layer, the upper oxide film and the nitride film in a portion in which a source region and a drain region will be formed, and injecting impurity ions into the semiconductor substrate at a portion in which the lower oxide film remains to form a source region and a drain region; after removing the remained lower oxide film, sequentially forming a third polysilicon layer and a tungsten silicide layer on the entire structure and then patterning the third polysilicon layer and the tungsten suicide layer to form a control gate; and performing an annealing process for activating the impurity ions injected into the source region and the drain region.
The device separation film is removed preferably by a wet etching process using HF solution of a 50:1 concentration. The floating gate is patterned in the X and Y directions so that it can have an independent shape. The dielectric film and the second polysilicon layer are preferably formed by low-pressure chemical vapor deposition method.
Also the upper oxide film and the nitride film are removed by plasma etching process. The lower oxide film remains in an amorphous state. The annealing process is preferably performed by rapid thermal process (RTP) under nitrogen (N2) atmosphere.